FIGS. 12 and 13 illustrates exemplary configuration and flowchart which is studied by the inventor. A configuration of the cache control used in the processor of the single thread system is illustrated in FIG. 12.
Reference sign 100 illustrated in the FIG. 12 denotes an instruction control unit, 200 denotes a cache control unit, 201 denotes a cache RAM, 202 denotes a fetch port (FP), 203 denotes a TOQ (Top-Of-Queue) control circuit, and 204 denotes a priority control circuit.
As illustrated in FIG. 12, requests for cache access from the instruction control unit 100 are once held in the fetch port 202 having plural entries present in the cache control unit 200.
The respective access requests are allocated to the fetch port 202 in order according to the order on a program. Each of entries of the fetch port 202 is circulatingly used. For example, when the fetch port 202 has sixteen entries (FP#0 to FP#15), the respective access requests are allocated in order from FP#0, then, are allocated to FP#0 again after one access request has been allocated to FP#15.
Each of the entries of the fetch port 202 holds one of the access requests until requested cache access processing is completed, then releases the allocated access request at a point when the requested cache access request is completed. An oldest entry number of the fetch port 202 for which the processing is not completed is indicated by a FP-TOQ (Fetch-Port-Top-Of-Queue) output by the TOQ control circuit 23.
When cache access is processed in “out of order”, selection of entries of the fetch port 202 that is read out for the cache access processing does not always need to depend on order of allocation of the fetch port 202. Basically, an access request for an arbitrary entry may be selected and processed. However, actually, entries are selected in order of priority provided by the priority control circuit 204.
Control processing in priority order executed by the priority control circuit 204 is illustrated in FIG. 13.
Specifically, when there exist one or more entries for which cache access is never performed yet or for which reprocessing is instructed to respond to an access request which has been put on standby in the fetch port 202 because of cache mistake, sequence guarantee for data and the like, an entry closest to the FP-TOQ among those entries is preferentially selected.
Secondly, when access request is allocated although not satisfying the condition of the first priority order, i.e., when one or more effective entries are present, an entry closest to the FP-TOQ among those entries is preferentially selected.
Such cache control used in the processor of the conventional SMT system is realized by directly using the cache control used in the processor of the single thread system configured as explained above.
Specifically, in the cache control used in the processor of the conventional SMT system, a fetch port having a specified number of entries for each of threads is provided. Access requests having highest priority order are selected for the respective threads according to priority order control illustrated in FIG. 13. An access request is finally selected out of the access requests by performing priority order control among the threads.
As a technique related to the present invention, in Patent Document 1 described below, an invention for realizing guarantee of consistency of execution order for readout and writing of shared data among threads in the processor of the SMT system is described.
Patent Document 1: International Publication WO2004/068361
As described above, the cache control used in the processor of the conventional SMT system is realized by directly using the cache control used in the processor of the single thread system. A fetch port having a specified number of entries for each of threads is provided. Access requests having highest priority order are selected for the respective threads according to priority order control illustrated in FIG. 13. An access request is finally selected out of the access requests by performing priority order control among the threads.
However, according to such a related art, there is a problem in that an increase in resources necessary for the cache access processing is inevitable.
Specifically, when the cache control used in the processor of the conventional SMT system is a cache control used in a processor of a single thread system in which, for example, a fetch port having sixteen entries is used in the processor, if the number of threads is n, n fetch ports having sixteen entries are prepared. Therefore, an increase in resources is inevitable.
Further, in the related art, there is a problem in that resources necessary for the cache access processing are not efficiently used.
Specifically, if explained concerning the case of two threads, it occurs that a frequency of access requests issued by one thread is higher than a frequency of access requests issued by the other thread.
Even when it is known from the beginning that such a situation occurs, in the related art, for example, a fetch port having sixteen entries is prepared for one thread and a fetch port having the same sixteen entries is prepared for the other thread.
Consequently, the fetch port prepared for the thread that issues a small number of access requests has entries more than necessary. Therefore, the fetch port is not efficiently used.
Further, it may occur that frequencies of access requests issued by the threads change according to the progress of data processing.
Even when such a situation occurs, in the related art, a fetch port having a fixed number of entries such as a fetch port having sixteen entries is prepared for the two threads.
Consequently, even when a frequency of access requests issued by one thread increases to be higher than a frequency of access requests issued by the other thread, the fetch port having the same number of entries is used irrespective of the increase in the frequency. Therefore, the fetch port is not efficiently used.